QUEFORMAL

The QUEFORMAL project proposes a radical vision of a new integrated circuit technology for machine learning where low-voltage field-effect transistors and non-volatile memories are integrated next to each other exploiting quantum engineering of heterostructures of two-dimensional materials (2DMs), i.e. the atom-by-atom design and fabrication of devices, which combine vertical and lateral heterostructures of 2DMs.

Our vision is based on the insight that heterostructures of 2D materials (in particular Transition Metal Dichalcogenides) provide a unique opportunity to engineer new materials almost atom by atom, essentially eliminating the boundary between electronic materials and devices.

QUEFORMAL project aims to demonstrate fabrication and operation of devices for logic-in-memory integrated circuits based on vertical and lateral heterostructures of 2DMs and to show the potential of this technology for integrated circuits for embedded Machine Learning (ML) capabilities.

Devices include i) lateral heterostructure FETs (LH-FETs) operating at low voltage fabricated in close vicinity to ii) floating-gate non-volatile memories based on vertical heterostructures (VHs) for the gate stack and LHs for the channel (LVH-NVMs).

This technology could open the way for industrial-level exploitation of quantum-engineered materials based on TMDCs, graphene, and other 2DMs for the fabrication of integrated nanoelectronic circuits for machine learning applications.

LATERAL AND VERTICAL HETEROSTRUCTURES

Different 2D materials (2DMs) can be combined within the same device and form diverse heterostructures. Each material has different electronic structure and properties, giving to the heterostructure new features and making it capable of enhancing properties, which are rather weak or nonexistent in their pristine counterparts. Lateral Heterostructures (LHs) of 2DMs consist of a single or few atom layer where domains of different 2DMs are laterally juxtaposed, often with quasi perfect lattice matching.

Vertical Heterostructures (VHs) of 2DMs are formed by vertically stacking layers of 2DMs and can enable the fabrication of gate stacks with a sequence of materials with different properties and controlled at the level of single atomic layer. Therefore they can enable the fabrication of floating-gate non-volatile memories (NVMs) where a LH-FET has a gate stack consisting of a VH with a 2DM floating gate, that we call LVH-NVMs. They require a relatively short retention time (1 month), because non-volatility is only needed to suppress static power consumption, allowing thin tunnel dielectrics and low program/erase voltage (5 V).

MULTISCALE MODELLING

From the theoretical point of view, ab-initio simulations of FETs based on LHs of different TMDCs, can be performed. Such simulations are important and useful for the integrated materials and device modeling and for the design of complete transistors based on LHs and on gate stacks of TMDCs. The principal aim is the development of a hierarchical multiscale computational protocol able to keep within a unique, integrated framework the realistic simulation of the whole LH/VH-based technology, from materials synthesis and properties to their integration into functional device operation.

MACHINE LEARNING

This project can represent the foundation of a revolutionary technology for specialized machine learning (ML) hardware. The nature of computing is evolving very rapidly. The recent breakthroughs of DNNs in image and language recognition, mainly ascribed to increasing computing power and abundance of data, have fueled the interest in artificial intelligence, and – in particular – in ML applications. However, the present reality of ML is that algorithms run on huge data centers, consuming large amounts of energy. Dedicated hardware for machine learning is being developed with the awareness that CMOS technology does not provide adequate improvement in energy efficiency and performance to keep the pace with the increase in size of deep neural networks, and it is also clear that memory has to be local in order to avoid access to DRAM or to SRAM cache which is orders of magnitude more costly in terms of energy consumption. Device and circuits modeling will allow us to benchmark the proposed technology, considering possible optimization beyond the project scope but based on project results, with respect to other proposed solutions considering the synthesis of a well known deep neural network system, such as AlexNet (5 levels, 650,000 neurons, 60M parameters).

The QUEFORMAL consortium consists of six partners. Consortium members have proposed and patented the LH-FET concept and have experimentally demonstrated the floating gate non-volatile memory concept using 2D materials.

UNIVERSITÀ DI PISA (UNIPI) (Project Coordinator)
Multiscale simulations of electronic devices and materials

GESELLSCHAFT FUR ANGEWANDTE MIKRO UND OPTOELEKTRONIK MIT BESCHRANKTERHAFTUNG (AMO)
Fabrication of heterostructures and device building blocks

UNIVERSITÄT DER BUNDESWEHR MÜNCHEN (UniBwM)
Fabrication and characterization of heterostructures

ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE (EPFL)
Fabrication and characterization of heterostructures

CONSIGLIO NAZIONALE DELLA RICERCA (CNR)
Ab-initio simulations of materials and contact modeling

QUANTAVIS
Device and circuit modeling and design